MC68HC711D3_05 Datasheet, PDF (88/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

Programmable Timer
MCU E
CLOCK
PRESCALER — DIVIDE BY
1, 4, 8, 16
PR1 PR0
16-BIT TIMER BUS
16-BIT COMPARATOR =
TOC1 (HI) TOC1 (LO)
16-BIT COMPARATOR =
TOC2 (HI) TOC2 (LO)
16-BIT COMPARATOR =
TOC3 (HI) TOC3 (LO)
16-BIT COMPARATOR =
TOC4 (HI) TOC4 (LO)
16-BIT COMPARATOR =
TI4/O5 (HI) TI4/O5 (LO)
16-BIT LATCH CLK
16-BIT LATCH CLK
TIC1 (HI) TIC1 (LO)
16-BIT LATCH CLK
TIC2 (HI) TIC2 (LO)
16-BIT LATCH CLK
TIC3 (HI) TIC3 (LO)
I4/O5
TCNT (HI) TCNT (LO)
TOI
16-BIT FREE RUNNING
TOF
COUNTER
OC1F
TAPS FOR RTL,
COP WATCHDOG,
AND PULSE ACCUMULATOR
FORCE
OUTPUT
OC1I
COMPARE
9
INTERRUPT REQUESTS
(FURTHER QUALIFIED
BY I BIT IN CCR)
TO PULSE
ACCUMULATOR
8
FOC1
BIT 7
OC2I
7
OC2F
BIT 6
FOC2
OC3I
6
OC3F
BIT 5
FOC3
OC4F
OC4I
FOC4
5
BIT 4
I4/O5I
4
OC5
I4/O5F
IC4
IC1F
IC2F
IC3F
FOC5
CFORC
IC1I
IC2I
IC3I
BIT 3
3
BIT 2
2
BIT 1
1
BIT 0
TFLG 1
STATUS
FLAGS
TMSK 1
INTERRUPT
ENABLES
PORT A
PIN
CONTROL
PORT A
PINS
PA7/OC1/
PAI
PA6/OC2/
OC1
PA5/OC3/
OC1
PA4/OC4/
OC1
PA3/IC4/
OC5/OC1
PA2/IC1
PA1/IC2
PA0/IC3
Figure 8-2. Capture/Compare Block Diagram
The control and status bits that implement the input capture functions are contained in the PACTL,
TCTL2, TMSK1, and TFLG1 registers.
To configure port A bit 3 as an input capture, clear the DDRA3 bit of the PACTL register. Note that this bit
is cleared out of reset. To enable PA3 as the fourth input capture, set the I4/O5 bit in the PACTL register.
Otherwise, PA3 is configured as a fifth output compare out of reset, with bit I4/O5 being cleared. If the
DDRA3 bit is set (configuring PA3 as an output), and IC4 is enabled, then writes to PA3 cause edges on
the pin to result in input captures. Writing to TI4/O5 has no effect when the TI4/O5 register is acting as IC4.
MC68HC711D3 Data Sheet, Rev. 2.1
88
Freescale Semiconductor