MC68HC711D3_05 Datasheet, PDF (83/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

Bits 3–0 — Not implemented
Always reads 0
SPI Registers
7.7.3 SPI Data I/O Register
The SPI data I/O register (SPDR) is used when transmitting or receiving data on the serial bus. Only a
write to this register initiates transmission or reception of a byte, and this only occurs in the master device.
At the completion of transferring a byte of data, the SPIF status bit is set in both the master and slave
devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun and the loss of the byte that
caused the overrun, the first SPIF must be cleared by the time a second transfer of data from the shift
register to the read buffer is initiated.
Address: $002A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Unaffected by reset
Figure 7-5. SPI Data I/O Register (SPDR)
NOTE
SPI is double buffered in and single buffered out.
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
83