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MC68HC711D3_05 Datasheet, PDF (135/138 Pages) Freescale Semiconductor, Inc – Microcontrollers
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MC68L11D0 Electrical Characteristics
B.2.6 Serial Peripheral Interface Timing
Num
Characteristic(1)
Symbol
1.0 MHz
Min Max
2.0 MHz
Unit
Min Max
Operating frequency
Master
Slave
fop(m)
fop(s)
dc
0.5
dc
0.5
fop
dc
1.0
dc
2.0 MHz
Cycle time
1 Master
Slave
Enable lead time
2
Master(2)
Slave
Enable lag time
3
Master(2)
Slave
tcyc(m)
2.0
—
2.0
—
tcyc
tCYC(s)
1000
—
500
—
ns
tlead(m)
—
—
—
—
ns
tlead(s)
500
—
250
—
tlag(m)
—
—
—
—
ns
tlag(s)
500
—
250
—
Clock (SCK) high time
4 Master
Slave
tw(SCKH)m 680
—
340
—
ns
tw(SCKH)s
380
—
190
—
Clock (SCK) low time
5 Master
Slave
tw(SCKL)m 680
—
340
—
ns
tw(SCKL)s
380
—
190
—
Data setup time (inputs)
6 Master
Slave
Data hold time (inputs)
7 Master
Slave
8
Access time (time to data active from high-impedance state)
Slave
9
Disable time (hold time to high-impedance state)
Slave
10 Data valid (after enable edge)(3)
11 Data hold time (outputs) (after enable edge)
Rise time (20% VDD to 70% VDD, CL = 200 pF)
12 SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
Fall time (70% VDD to 20% VDD, CL = 200 pF)
13 SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tsu(m)
tsu(s)
th(m)
th(s)
ta
tdis
tv(s)
tho
trm
trs
tfm
tfs
100
—
100
—
ns
100
—
100
—
100
—
100
—
ns
100
—
100
—
0
120
0
120 ns
—
240
—
240 ns
—
240
—
240 ns
0
—
0
—
ns
—
100
—
100 ns
—
2.0
—
2.0 µs
—
100
—
100 ns
—
2.0
—
2.0 µs
1. VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted.
2. Signal production depends on software.
3. Assumes 100 pF load on all SPI pins.
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
135
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