MC68HC711D3_05 Datasheet, PDF (101/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

TMSK2 INT ENABLES
E ÷ 64 CLOCK
(FROM MAIN TIMER)
PA7/
PAI/OC1
INPUT BUFFER
AND
EDGE DETECTION
FROM
MAIN TIMER
OC1
OUTPUT
BUFFER
Pulse Accumulator
1
INTERRUPT
REQUESTS
2
TFLG2 INTERRUPT STATUS
PAI EDGE
DISABLE
FLAG SETTING
OVERFLOW
2:1
MUX
PACNT
8-BIT COUNTER
ENABLE
PAEN
PACTL CONTROL
INTERNAL
DATA BUS
Figure 8-19. Pulse Accumulator
Table 8-7. Pulse Accumulator Timing in Gated Mode
CPU Clock
Cycle Time
(E/2⁶)
(E/2¹⁴)
Selected
Crystal
(E)
(1/E)
1 count -
overflow -
Common XTAL Frequencies
4.0 MHz
1.0 MHz
1000 ns
8.0 MHz
2.0 MHz
500 ns
12.0 MHz
3.0 MHz
333 ns
64.0 µs
16.384 ms
32.0 µs
8.192 ms
21.33 µs
5.461 ms
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
101