MC68HC711D3_05 Datasheet, PDF (96/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

Programmable Timer
8.4.8 Timer Interrupt Flag 1 Register
The timer interrupt flag 1 register (TFLG1) bits indicate when timer system events have occurred. Coupled
with the bits of TMSK1, the bits of TFLG1 allow the timer subsystem to operate in either a polled or
interrupt driven system. Each bit of TFLG1 corresponds to a bit in TMSK1 in the same position.
Address: $0023
Bit 7
6
5
4
3
2
1
Bit 0
Read:
OC1F
OC2F
OC3F
OC4F I4/O5F
IC1F
IC2F
IC3F
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 8-13. Timer Interrupt Flag 1 Register (TFLG1)
Clear flags by writing a 1 to the corresponding bit position(s).
OC1F–OC5F — Output Compare x Flag
Set each time the counter matches output compare x value
I4/O5F — Input Capture 4/Output Compare 5 Flag
Set by IC4 or OC5, depending on the function enabled by I4/O5 bit in PACTL
IC1F–IC3F — Input Capture x Flag
Set each time a selected active edge is detected on the ICx input line
8.4.9 Timer Interrupt Mask 2 Register
The timer interrupt mask 1 register (TMSK2) is an 8-bit register used to enable or inhibit timer overflow
and real-time interrupts. The timer prescaler control bits are included in this register.
Address: $0024
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TOI
RTII
PAOVI
PAII
0
Write:
0
PR1
PR0
Reset: 0
0
0
0
0
0
0
0
Figure 8-14. Timer Interrupt Mask 2 Register (TMSK2)
TOI — Timer Overflow Interrupt Enable Bit
0 = TOF interrupts disabled
1 = Interrupt requested when TOF is set to 1
RTII — Real-Time Interrupt Enable Bit
Refer to 8.5 Real-Time Interrupt.
PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit
Refer to 8.7 Pulse Accumulator.
PAII — Pulse Accumulator Input Edge Interrupt Enable Bit
Refer to 8.7 Pulse Accumulator.
NOTE
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2
enable the corresponding interrupt sources.
MC68HC711D3 Data Sheet, Rev. 2.1
96
Freescale Semiconductor