MC68HC711D3_05 Datasheet, PDF (98/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

Programmable Timer
8.5 Real-Time Interrupt
The real-time interrupt feature, used to generate hardware interrupts at a fixed periodic rate, is controlled
and configured by two bits (RTR1 and RTR0) in the pulse accumulator control (PACTL) register. The RTII
bit in the TMSK2 register enables the interrupt capability. The four different rates available are a product
of the MCU oscillator frequency and the value of bits RTR1 and RTR0. Refer to Table 8-5 for the periodic
real-time interrupt rates.
Table 8-5. Periodic Real-Time Interrupt Rates
RTR1
and RTR0
00
01
10
11
E = 1 MHz
2.731 ms
5.461 ms
10.923 ms
21.845 ms
E = 2 MHz
4.096 ms
8.192 ms
16.384 ms
32.768 ms
E = 3 MHz
8.192 ms
16.384 ms
32.768 ms
65.536 ms
E = X MHz
(E/2¹³)
(E/2¹⁴)
(E/2¹⁵)
(E/2¹⁶)
The clock source for the RTI function is a free-running clock that cannot be stopped or interrupted except
by reset. This clock causes the time between successive RTI timeouts to be a constant that is
independent of the software latencies associated with flag clearing and service. For this reason, an RTI
period starts from the previous timeout, not from when RTIF is cleared.
Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt request is generated.
After reset, one entire real-time interrupt period elapses before the RTIF flag is set for the first time. Refer
to the TMSK2, TFLG2, and PACTL registers.
8.5.1 Timer Interrupt Mask 2 Register
The timer interrupt mask 2 register (TMSK2) contains the real-time interrupt enable bits.
Address: $0024
Bit 7
6
5
4
3
Read:
TOI
RTII
PAOVI
PAII
0
Write:
Reset: 0
0
0
0
0
2
1
Bit 0
0
PR1
PR0
0
0
0
Figure 8-16. Timer Interrupt Mask 2 Register (TMSK2)
TOI — Timer Overflow Interrupt Enable Bit
Refer to 8.4 Output Compare (OC).
RTII — Real-Time Interrupt Enable Bit
0 = RTIF interrupts disabled
1 = Interrupt requested
PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit
Refer to 8.7 Pulse Accumulator.
PAII — Pulse Accumulator Input Edge Bit
Refer to 8.7 Pulse Accumulator.
Bits 3–2 — Unimplemented
Always read 0.
MC68HC711D3 Data Sheet, Rev. 2.1
98
Freescale Semiconductor