MC68HC711D3_05 Datasheet, PDF (16/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

General Description
PC4
1
PC5
2
PC6
3
PC7
4
XIRQ
5
PD7
6
PD6
7
RESET
8
IRQ
9
PD0
10
PD1
PB0
32
PB1
31
PB2
30
PB3
29
PB4
28
PB5
27
PB6
26
PB7
25
NC
24
PA0
23
PA1
Figure 1-4. Pin Assignments for 44-Pin QFP
1.5 Power Supply (V_DD, V_SS, and EV_SS)
Power is supplied to the MCU through V_DD and V_SS. V_DD is the power supply (+5 V ±10%) and V_SS is
ground (0 V). EV_SS, available on the 44-pin PLCC and QFP, is an additional ground pin.
1.6 Reset (RESET)
An active low bidirectional control signal, RESET, acts as an input to initialize the MCU to a known startup
state. It also acts as an open-drain output to indicate that an internal failure has been detected in either
the clock monitor or computer operating properly (COP) watchdog circuit. In addition, the state of this pin
is one of the factors governing the selection of BOOT mode.
1.7 Crystal Driver and External Clock Input (XTAL and EXTAL)
These two pins provide the interface for either a crystal or a CMOS compatible clock to control the internal
clock generator circuitry. The frequency applied to these pins is four times higher than the desired E-clock
rate. Refer to Figure 1-5 for crystal and clock connections.
1.8 E-Clock Output (E)
E is the output connection for the internally generated E clock. The signal from E is used as a timing
reference. The frequency of the E-clock output is one fourth that of the input frequency at the XTAL and
EXTAL pins. The E clock can be turned off in single-chip mode for greater noise immunity if desired. See
4.3.6 Highest Priority I Interrupt and Miscellaneous Register (HPRIO) for details.
MC68HC711D3 Data Sheet, Rev. 2.1
16
Freescale Semiconductor