MC68HC711D3_05 Datasheet, PDF (117/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

9.9 Serial Peripheral Interface Timing
Serial Peripheral Interface Timing
Num
Characteristic⁽¹⁾
2.0 MHz 3.0 MHz
Symbol
Unit
Min Max Min Max
Operating frequency
Master
Slave
f_op(m)
f_op(s)
dc 0.5 dc 0.5 f_op
dc 2.0 dc 3.0 MHz
Cycle time
1 Master
Slave
Enable lead time
2
Master⁽²⁾
Slave
Enable lag time
3
Master⁽²⁾
Slave
t_cyc(m)
t_CYC(s)
2.0 — 2.0 — t_cyc
500 — 333 — ns
t_lead(m)
— — — — ns
t_lead(s) 250 — 240 —
t_lag(m)
t_lag(s)
— — — — ns
250 — 240 —
Clock (SCK) high time
4 Master
Slave
Clock (SCK) low time
5 Master
Slave
t_{w(SCKH)m 340 — 227 — ns}
t_w(SCKH)s 190 — 127 —
t_{w(SCKL)m 340 — 227 — ns}
t_w(SCKL)s 190 — 127 —
Data setup time (inputs)
6 Master
Slave
t_su(m)
t_su(s)
100 — 100 — ns
100 — 100 —
Data hold time (inputs)
7 Master
Slave
8
Access time (time to data active from high-impedance state)
Slave
9
Disable time (hold time to high-impedance state)
Slave
10 _{Data valid (after enable edge)}⁽³⁾
11 Data hold time (outputs) (after enable edge)
Rise time (20% V_DD to 70% V_DD, C_L = 200 pF)
12 SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
Fall time (70% V_DD to 20% V_DD, C_L = 200 pF)
13 SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
t_h(m)
t_h(s)
t_a
t_dis
t_v(s)
t_ho
100 — 100 — ns
100 — 100 —
0 120 0 120 ns
— 240 — 167 ns
— 240 — 167 ns
0 — 0 — ns
t_rm
— 100 — 100 ns
t_rs
— 2.0 — 2.0 µs
t_fm
— 100 — 100 ns
t_fs
— 2.0 — 2.0 µs
1. V_DD = 5.0 Vdc ± 10%, V_SS = 0 Vdc, T_A = T_L to T_H. All timing is shown with respect to 20% V_DD and 70% V_DD, unless
otherwise noted.
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins.
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
117