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MC68HC711D3_05 Datasheet, PDF (134/138 Pages) Freescale Semiconductor, Inc – Microcontrollers
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MC68L11D0
B.2.5 Expansion Bus Timing
Num
Characteristic(1)
Symbol
1.0 MHz
Min
Max
2.0 MHz
Unit
Min Max
Frequency of operation (E-clock frequency)
1 Cycle time
2 Pulse width, E low, PWEL = 1/2 tcyc — 23 ns
3 Pulse width, E high, PWEH = 1/2 tcyc – 28 ns
4A E and AS rise time
4B E and AS fall time
9 Address hold time(2)a, tAH = 1/8 tcyc – 29.5 ns
Non-muxed address valid time to E rise
12
tAV = PWEL – (tASD + 80 ns)(2)a
17 Read data setup time
18 Read data hold time (max = tMAD)
19 Write data delay time, tDDW = 1/8 tcyc + 65.5 ns(2)a
21 Write data hold time, tDHW = 1/8 tcyc – 29.5 ns(2)a
Muxed address valid time to E rise
22
tAVM = PWEL – (tASD + 90 ns)(2)a
Muxed address valid time to AS fall
24 tASL = PWASH – 70 ns
25 Muxed address hold time, tAHL = 1/8 tcyc – 29.5 ns(2)b
26 Delay time, E to AS rise, tASD = 1/8 tcyc – 9.5 ns(2)a
27 Pulse width, AS high, PWASH = 1/4 tcyc – 29 ns
28 Delay time, AS to E rise, tASED = 1/8 tcyc – 9.5 ns(2)b
29
MPU address access time(2)a
tACCA = tcyc – (PWEL– tAVM) – tDSR – tf
35 MPU access time , tACCE = PWEH – tDSR
Muxed address delay (previous cycle MPU read)
36
tMAD = tASD + 30 ns(2)a
fO
tcyc
PWEL
PWEH
tr
tf
tAH
tAV
tDSR
tDHR
tDDW
tDHW
tAVM
dc
1000
475
470
—
—
95
275
30
0
—
95
265
tASL
150
tAHL
95
tASD
120
PWASH 220
tASED
120
tACCA
735
tACCE
—
tMAD
150
1.0
dc 2.0 MHz
—
500 —
ns
—
225 —
ns
—
220 —
ns
25
— 25
ns
25
— 25
ns
—
33 —
ns
—
88 —
ns
—
30 —
ns
150
0
88
ns
195
— 133 ns
—
33 —
ns
—
78 —
ns
—
25 —
ns
—
33 —
ns
—
58 —
ns
—
95 —
ns
—
58 —
ns
—
298 —
ns
440
— 190 ns
—
88 —
ns
1. VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted.
2. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle
are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place
of 1/8 tCYC in the above formulas, where applicable:
(a) (1-dc) × 1/4 tCYC
(b) dc × 1/4 tCYC
Where:
DC is the decimal value of duty cycle percentage (high time).
MC68HC711D3 Data Sheet, Rev. 2.1
134
Freescale Semiconductor
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