MC68HC711D3_05 Datasheet, PDF (109/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

9.6 Control Timing
Control Timing
Characteristic⁽¹⁾
Symbol
1.0 MHz
2.0 MHz 3.0 MHz
Unit
Min Max Min Max Min Max
Frequency of operation
E-clock period
Crystal frequency
External oscillator frequency
Processor control setup timet_PCSU = 1/4 t_cyc + 50 ns
Reset input pulse width⁽²⁾
To guarantee external reset vector
Minimum input time can be preempted by internal reset
f_O
t_cyc
f_XTAL
4 f_O
t_PCSU
dc 1.0 dc 2.0 dc 3.0 MHz
1000 — 500 — 333 — ns
— 4.0 — 8.0 — 12.0 MHz
dc 4.0 dc 8.0 dc 12.0 MHz
300 — 175 — 133 — ns
PW_RSTL
8
1
— 8 — 8 — t_cyc
—1—1—
Mode programming setup time
Mode programming hold time
Interrupt pulse width, PW_IRQ = t_cyc + 20 ns
IRQ edge-sensitive mode
t_MPS
t_MPH
2
— 2 — 2 — t_cyc
10 — 10 — 10 — ns
PW_IRQ 1020 — 520 — 353 — ns
Wait recovery startup time
Timer pulse width PW_TIM = t_cyc + 20 ns
Input capture pulse
Accumulator input
t_WRS
—
4 — 4 — 4 t_cyc
PW_TIM 1020 — 520 — 353 — ns
1. V_DD = 5.0 Vdc ± 10%, V_SS = 0 Vdc, T_A = T_L to T_H. All timing is shown with respect to 20% V_DD and 70% V_DD, unless
otherwise noted.
2. Reset is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles,
releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to Chapter 5
Input/Output (I/O) Ports for further details.
PA0–PA3⁽¹⁾
PA0–PA3⁽²⁾
PA7^{(1) (3)}
PA7^{(2) (3)}
PW_TIM
Notes:
1. Rising edge sensitive input
2. Falling edge sensitive input
3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.
Figure 9-3. Timer Inputs
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
109