MC68HC711D3_05 Datasheet, PDF (35/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

CPU Registers
JSR, JUMP TO SUBROUTINE
MAIN PROGRAM
PC
$9D = JSR
DIRECT
dd
RTN NEXT MAIN INSTR
MAIN PROGRAM
PC
$AD = JSR
INDXD,X
ff
RTN NEXT MAIN INSTR
MAIN PROGRAM
PC
$18 = PRE
INDXD,Y
$AD = JSR
ff
RTN NEXT MAIN INSTR
MAIN PROGRAM
PC
$BD = JSR
hh
EXTEND
ll
RTN NEXT MAIN INSTR
BSR, BRANCH TO SUBROUTINE
MAIN PROGRAM
PC
$8D = BSR
rr
RTN NEXT MAIN INSTR
RTS, RETURN FROM SUBROUTINE
SUBROUTINE
PC
$39 = RTS
SWI, SOFTWARE INTERRUPT
MAIN PROGRAM
PC
$3F = SWI
RTN
WAI, WAIT FOR INTERRUPT
MAIN PROGRAM
PC
$3E = WAI
RTN
STACK
SP-2
SP-1
RTN_L
SP
RTN_H
RTI, RETURN FROM INTERRUPT
INTERRUPT PROGRAM
STACK
PC
$3B = RTI
SP
SP+1 CONDITION CODE
SP+2
ACMLTR B
SP+3
ACMLTR A
SP+4 INDEX REGISTER (X_H)
SP+5 INDEX REGISTER (X_L)
SP+6 INDEX REGISTER (Y_H)
SP+7 INDEX REGISTER (Y_L)
SP+8
RTN_L
SP+9
RTN_H
JMP, JUMP
PC
MAIN PROGRAM
$6E = JMP
ff
INDXD,X
STACK
SP-2
SP-1
RTN_L
SP
RTN_H
SP
SP+1
SP+2
STACK
RTN_L
RTN_H
X + ff NEXT INSTRUCTION
INDXD,Y
MAIN PROGRAM
PC
$18 = PRE
$6E = JMP
ff
EXTND
X + ff NEXT INSTRUCTION
MAIN PROGRAM
PC
$7E = JMP
hh
ll
STACK
SP-9
SP-8 CONDITION CODE
SP-7
ACMLTR B
SP-6
ACMLTR A
SP-5 INDEX REGISTER (X_H)
SP-4 INDEX REGISTER (X_L)
SP-3 INDEX REGISTER (Y_H)
SP-2 INDEX REGISTER (Y_L)
SP-1
RTN_L
SP
RTN_H
hh ll NEXT INSTRUCTION
LEGEND:
RTN Address of next instruction in main program to be
executed upon return from subroutine
RTN_H Most significant byte of return address
RTN_L Least significant byte of return address
Shaded cells show stack pointer position after
operation is complete.
dd 8-bit direct address ($0000–$00FF) (high byte
assumed to be $00).
ff 8-bit positive offset $00 (0) to $FF (256) is added
to index.
hh High-order byte of 16-bit extended address.
ll Low-order byte of 16-bit extended address.
rr Signed-relative offset $80 (–128) to $7F (+127)
(offset relative to the address following the
machine code offset byte).
Figure 3-2. Stacking Operations
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
35