MC68HC711D3_05 Datasheet, PDF (59/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

Interrupts
Mode
IRVNE E Clock IRV IRVNE IRVNE
Out
Out
Out Affects May
of Reset of Reset of Reset Only be Written
Single chip
0
On
Off
E
Once
Expanded multiplexed
0
On
Off
IRV
Once
Bootstrap
0
On
Off
E
Once
Special test
1
On
On
IRV
Once
NOTE
To prevent bus conflicts, when using internal read visibility, the user must
disable all external devices from driving the data bus during any internal
access.
PSEL3–PSEL0 — Priority Selects
These four bits are used to specify one I bit related interrupt source, which then becomes the highest
priority I bit related interrupt source. These bits may be written only while the I bit in the CCR is set,
inhibiting I bit related interrupts. An interpretation of the value of these bits is shown in Table 4-4.
During reset, PSEL3–PSEL0 are initialized to 0101, which corresponds to reserved (default to IRQ).
IRQ becomes the highest priority I bit related interrupt source.
Table 4-4. Highest Priority Interrupt Selection
PSEL3–PSEL0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Interrupt Source Promoted
Timer overflow
Pulse accumulator overflow
Pulse accumulator input edge
SPI serial transfer complete
SCI serial system
Reserved (default to IRQ)
IRQ (external pin)
Real-time interrupt
Timer input capture 1
Timer input capture 2
Timer input capture 3
Timer output compare 1
Timer output compare 2
Timer output compare 3
Timer output compare 4
Timer input capture 4/output compare 5
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
59