MC68HC711D3_05 Datasheet, PDF (44/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

Central Processor Unit (CPU)
Table 3-2. Instruction Set (Sheet 6 of 8)
Mnemonic
Operation
Description
Addressing
Mode
Instruction
Condition Codes
Opcode Operand Cycles S X H I N Z V C
LSRD
Logical Shift
INH
Right Double ₀
b7 A b0 b7 B b0 C
MUL
Multiply 8 by 8
A∗B⇒D
INH
04
—
3D
—
3
———— 0 ∆ ∆ ∆
10 — — — — — — — ∆
NEG (opr)
Two’s
Complement
Memory Byte
0–M⇒M
EXT
IND,X
IND,Y 18
70 hh ll
60 ff
60 ff
6
———— ∆ ∆ ∆ ∆
6
7
NEGA
Two’s
Complement
A
0–A⇒A
A
INH
40
—
2
———— ∆ ∆ ∆ ∆
NEGB
Two’s
Complement
B
0–B⇒B
B
INH
50
—
2
———— ∆ ∆ ∆ ∆
NOP
No operation
No Operation
INH
01
—
2
————————
ORAA (opr)
OR
Accumulator
A (Inclusive)
A+M⇒A
A
IMM
8A ii
A
DIR
9A dd
A
EXT
BA hh ll
A
IND,X
AA ff
A
IND,Y 18
AA ff
2
———— ∆ ∆ 0 —
3
4
4
5
ORAB (opr)
OR
Accumulator
B (Inclusive)
B+M⇒B
B
IMM
CA ii
B
DIR
DA dd
B
EXT
FA hh ll
B
IND,X
EA ff
B
IND,Y 18
EA ff
2
———— ∆ ∆ 0 —
3
4
4
5
PSHA
Push A onto A ⇒ Stk,SP = SP – 1 A
INH
Stack
36
—
3
————————
PSHB
Push B onto B ⇒ Stk,SP = SP – 1 B
INH
Stack
37
—
3
————————
PSHX
Push X onto IX ⇒ Stk,SP = SP – 2
INH
Stack (Lo
First)
3C
—
4
————————
PSHY
Push Y onto IY ⇒ Stk,SP = SP – 2
Stack (Lo
First)
INH
18
3C
—
5
————————
PULA
Pull A from SP = SP + 1, A ⇐ Stk A
INH
Stack
32
—
4
————————
PULB
Pull B from SP = SP + 1, B ⇐ Stk B
INH
Stack
33
—
4
————————
PULX
Pull X From SP = SP + 2, IX ⇐ Stk
INH
Stack (Hi
First)
38
—
5
————————
PULY
Pull Y from
Stack (Hi
First)
SP = SP + 2, IY ⇐ Stk
INH
18
38
—
6
————————
ROL (opr)
Rotate Left
C b7
b0
EXT
IND,X
IND,Y 18
79 hh ll
69 ff
69 ff
6
———— ∆ ∆ ∆ ∆
6
7
ROLA
Rotate Left A
A
INH
49
—
2
———— ∆ ∆ ∆ ∆
ROLB
Rotate Left B
C b7
b0
B
INH
59
—
2
———— ∆ ∆ ∆ ∆
ROR (opr) Rotate Right
RORA
Rotate Right A
C b7
b0
b7
b0 C
A
EXT
IND,X
IND,Y 18
INH
76 hh ll
66 ff
66 ff
46
—
6
———— ∆ ∆ ∆ ∆
6
7
2
———— ∆ ∆ ∆ ∆
RORB
Rotate Right B
b7
b0 C
B
INH
56
—
2
———— ∆ ∆ ∆ ∆
b7
b0 C
RTI
Return from
See Figure 3-2
INH
Interrupt
3B
—
12
∆↓∆∆∆∆∆∆
MC68HC711D3 Data Sheet, Rev. 2.1
44
Freescale Semiconductor