MC68HC711D3_05 Datasheet, PDF (70/138 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Communications Interface (SCI)
6.7.2 SCI Control Register 1
The SCI control register 1 (SCCR1) provides the control bits that determine word length and select the
method used for the wakeup feature.
Address: $002C
Bit 7
6
5
Read:
R8
T8
0
Write:
Reset: U
U
0
U = Unaffected
4
3
2
M
WAKE
0
0
0
0
1
Bit 0
0
0
0
0
Figure 6-4. SCI Control Register 1 (SCCR1)
R8 — Receive Data Bit 8
If M bit is set, R8 stores the ninth bit in the receive data character.
T8 — Transmit Data Bit 8
If M bit is set, T8 stores ninth bit in transmit data character.
M — Mode Bit
The mode bit selects character format
0 = Start bit, 8 data bits, 1 stop bit
1 = Start bit, 9 data bits, 1 stop bit
WAKE — Wakeup by Address Mark/Idle Bit
0 = Wakeup by IDLE line recognition
1 = Wakeup by address mark (most significant data bit set)
6.7.3 SCI Control Register 2
The SCI control register 2 (SCCR2) provides the control bits that enable or disable individual SCI
functions.
Address: $002D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 6-5. SCI Control Register 2 (SCCR2)
TIE — Transmit Interrupt Enable Bit
1 = TDRE interrupts disabled
1 = SCI interrupt requested when TDRE status flag is set
TCIE — Transmit Complete Interrupt Enable Bit
0 = TC interrupts disabled
1 = SCI interrupt requested when TC status flag is set
RIE — Receiver Interrupt Enable Bit
0 = RDRF and OR interrupts disabled
1 = SCI interrupt requested when RDRF flag or the OR status flag is set
MC68HC711D3 Data Sheet, Rev. 2.1
70
Freescale Semiconductor