C-3E Datasheet, PDF (98/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

98
CHAPTER 3: ELECTRICAL SPECIFICATIONS
QMU SRAM (Internal The QMU SRAM (Internal Mode) timing specifications are shown in Figure 26 and
Mode) Timing _{described in Table 53.}
Specifications
Cycle 1
Figure 26 QMU SRAM (Internal Mode) Timing Diagram
Cycle 2
Cycle 3
Cycle 4
Cycle 5
QACLKI
Q_ctl
QAn
QDn
(output)
T_qdo
QDn
(input)
T_qc
T_qco
T_qao
T_qdz
T_qdv
T_qds T_qdh
Table 53 QMU SRAM (Internal Mode) Timing Description
SYMBOL
Tqc
Tqco
PARAMETER
QMU Cycle Time
QMU Ctrl Output
MIN TYP MAX
6.7
0.8
4.4
Tqao QMU Addr Output 0.8
4.4
Tqds QMU Data Setup 0.8
Tqdh QMU Data Hold
0.8
Tqdo QMU Data Output 0.9
4.4
UNIT COMMENT
ns
ns
Loading is 50Ω
transmission line.
ns
Loading is 50Ω
transmission line.
ns
ns
ns
Loading is 50Ω
transmission line.
C3EN