C-3E Datasheet, PDF (49/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

Pin Descriptions Grouped by Function
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Fabric Processor Interface The FP has logical signal interfaces: a receive data interface and a transmit data interface,
Signals _{each with its own control, data, and clock signals. The interface has the following}
characteristic:
The interface clocks FRXCLK and FTXCLK can have a different frequency from the core
C-3e NP clock frequency. The FP supports a fabric interface frequency from 10MHz to
125MHz.
FRXCLK and FTXCLK can be independent of each other; typically they have the same
frequency, but are allowed to be skewed relative to each other.
Each data bus can be configured for widths of 8 (data bits 7:0 are used), or 16 (bits 15:0). In
8bit mode, data bits 15:8 are unused.
Table 19 Fabric Interface Signals
SIGNAL NAME
PIN #
FIN0 - FIN15
AD13, AC13, AB13, AG12, AF12, AE12, AD12,
AC12, AB12, AG11, AF11, AE11, AD11, AC11,
AB11, AG10
FOUT0 - FOUT15
AG17, AF17, AG16, AF16, AE16, AD16, AC16,
AB16, AG15, AF15, AE15, AD15, AC15, AB15,
AG14, AE14
FRXCLK
AG9
FTXCLK
AE13
FRXCTL0 - FRXCTL2 & AE10, AD10, AC10, AB10
FRXCTL6
FTXCTL0 - FRXCTL2 & AC14, AB14, AG13, AF13
FTXCTL6
TOTAL PINS
TOTAL TYPE I/O SIGNAL DESCRIPTION
16
LVTTL I_PD Fabric Data Bus In
16 LVTTL O Fabric Data Bus Out
1
LVTTL I_PD Receive Clock
1
LVTTL I_PD Transmit Clock
4
LVTTL I_PD, O Receive Control Signals
4
LVTTL I_PD, O Transmit Control Signals
42
The following tables list the Fabric Interface pin mappings:
• Utopia1, Utopia2, Utopia3 ATM Mode mappings are listed in Table 20
• Utopia1, Utopia2, Utopia3 PHY Mode mappings are listed in Table 21
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