C-3E Datasheet, PDF (47/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

Pin Descriptions Grouped by Function
47
XP PROM Interface outline
Q<
SPLD
SPDTO
A1
8 SPLD is deasserted for 22 SPCLK cycles, shifting the second PROM_DATA into the
network processor internal shift register.
9 SPLD is asserted for one SPCLK cycle, loading the second PROM_DATA into the
network processor PROM_RETURN_DATA register.
Figure 6 PROM Interface Timing Outline
Q<
Q<
Q<
‘
A2
A3
A4
A5
SPDTI
D1
D2
D3
XP PROM Interface detail
SPCLK
12
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7
SPLD
SPDTO
1
A1
x
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
The PROM_ADDR is loaded into the
C-5's internal shift register.
The PROM_ADDR is shifted into
the external shift register.
(SPCLK Rising Edge used for shifting)
2
SPDTI
A2
35
The PROM_ADDR is loaded into the
external presentation register.
The PROM_DATA is
presenting.
A3
A4
4
The PROM_DATA is loaded into the
external shift register.
D1
D2
x
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
x
x
x
x
x
x
68
The PROM_DATA is shifted into the C-5's
Internal shift register.
The PROM_DATA is loaded into the C-5's
7 9 internal PROM_RETURN_DATA register.
03