C-3E Datasheet, PDF (35/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

Pin Descriptions Grouped by Function
35
10/100 Ethernet (RMII) Configuration
Table 9 describes the 10/100BASE-T Ethernet Reduced Media Independent Interface
(RMII) signals. For each CP (0-15), you can implement one 10/100 Ethernet interface.
Table 9 10/100 Ethernet Signals
SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL
SIGNAL DESCRIPTION
CPn_0
CPn_1
Table 7 1
Table 7 1
LVTTL O_PD REF_CLK Transmit and Receive Clock (50MHz)
LVTTL I_PU CRS_DV Carrier Sense (CRS)/ Receive Data Valid (RX_DV). CRS indicates that
traffic is on the link, and is asserted if the signal is a 1 or an
alternating 1010... RX_DV indicates that a receive frame is in
progress and the data present on the RXD pins is valid. It is
asserted if this signal is a 1 for more than one cycle.
CPn_2
CPn_3
CPn_4
CPn_5
CPn_6
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
LVTTL O_PD TXD(0)
LVTTL O_PU TXD(1)
LVTTL I_PD RXD(0)
LVTTL I_PU RXD(1)
LVTTL O_PU TX_EN
Transmit Data 0 (first on wire)
Transmit Data 1 (second on wire)
Receive Data 0 (first on wire)
Receive Data 1 (second on wire)
Transmit Enable. When asserted, the data on TXD is encoded and
transmitted on the twisted pair cable.
TOTAL PINS
7
* _{n can be from 0 to 7. See Table 7.}
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