C-3E Datasheet, PDF (48/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

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CHAPTER 2: SIGNAL DESCRIPTIONS
General System Interface Signal
Table 18 provides the signal for the Executive Processor reset power status and I/O clock.
The C-3e NP can be powered up with the XP either running or with the XP in reset mode
similar to the CPs. When the XP remains in reset mode, an external host can be used to
control the initialization of the C-3e NP.
Table 18 General System Interface Signal
SIGNAL NAME
XPUHOT
TOTAL PINS
PIN #
Y3
TOTAL TYPE I/O
1
LVTTL I_PD
1
SIGNAL DESCRIPTION
Sample at Power On Reset determines if the XP RISC Core is held in reset. Low
equals reset and High equals active. During normal operation, this is an
external interrupt.
C3EN