C-3E Datasheet, PDF (26/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

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CHAPTER 1: FUNCTIONAL DESCRIPTION
Queue Management Unit
The Queue Management Unit (QMU) autonomously manages a number of
application-defined descriptor queues. It handles inter-CP and inter-C-3e NP descriptor
flows by providing switching and buffering. It also performs descriptor replication for
multicast applications. A number of up to 128 queues can be assigned to each CPRC for
QoS-based services.
The QMU provides a queuing engine internal to the chip and uses external SRAM to store
the descriptors. Scheduling is done by the CPs. The QMU supports up to 512 queues and
16, 384 descriptor buffers. A descriptor buffer holds an application-defined “descriptor”,
which is a structure that defines the payload buffer handle and other attributes of the
forwarded cell or packet.
The QMU’s external SRAM interface uses ZBT synchronous SRAMs organized in a single
bank of up to 128k, 32bit words. This interface runs at up to 150MHz frequency.
The C-3e provides two modes for managing queues. They consist of:
• Internal Mode (using the internal QMU only)
• External Mode (using the internal QMU and the external Q-5 Traffic Management
Coprocessor, or using the internal QMU and the external Q-3 Traffic Management
Coprocessor).
See the C-5e/C-3e Network Processor Architecture Guide (part number C5EC3EARCH-RM/D),
as well as, the Q-5/Q-3 Traffic Management Coprocessor Architecture Guide (part number
Q5Q3ARCH-RM/D) for more details.
C3EN