C-3E Datasheet, PDF (79/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

AC Timing Specifications
79
AC Timing Specifications
AC timing specifications consist of input requirements and output responses. The input
requirements include setup and hold times, pulse widths, and high and low times. The
output responses include delays from clock to signal. The AC timing specifications are
defined separately for each interface to the C-3e NP.
See Figure 12. Output timing specifications for LVTTL pins are given with a 20pF load on
the output. Other loads can be simulated with the IBIS model available from Motorola.
The LVPECL driver is specified into a 50Ω load terminated to a (VDD33 - 2V) reference.
Figure 12 Test Loading Conditions
LVTTL
DUT
20pF
LVPECL
DUT
VDD33
+2V
50Ω
03