C-3E Datasheet, PDF (57/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

Pin Descriptions Grouped by Function
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Test Signals Test signals are described in Table 27.
Table 27 Miscellaneous Test Signals For JTAG, Scan, and Internal Test Routines
SIGNAL NAME
JTCK
JTMS
PIN #
B17
A17
TOTAL TYPE I/O
1
LVTTL I_PD
1
LVTTL I_PD
JTRSTX
JTDI
JTDO
JHIGHZ
JCLKBYP
JSE
JS00-JS05
TOTAL PINS
A16
C16
C14
B15
A15
D15
C13, B13, A13, B14, A14, C15
1
LVTTL I_PD
1
LVTTL I_PD
1
LVTTL O
1
LVTTL I_PD
1
LVTTL I_PD
1
LVTTL I_PD
6
LVTTL O
14
SIGNAL DESCRIPTION
Test Clock
Test Mode Select. High selects modes
as defined in the IEEE 1149.1 JTAG
specification.
Test Reset (low active)
Test Data In
Test Data Out
Turns off all output drivers when High
1X or 2X Clock Mode Select. Low
selects 1X, High selects 2X.
Scan Enable. High enables scan test.
Scan Out Pins
During JTAG, SCLK and SCLKX must remain as differential inputs.
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