C-3E Datasheet, PDF (91/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

SPCK
SPDI
SPLD
SPDO
Cycle 1
AC Timing Specifications
91
PROM Interface Timing Specifications
The PROM interface timing is shown in Figure 22 and described in Table 47.
Figure 22 PROM Interface Timing Diagram
Cycle 2
Cycle 3
Cycle 4
Cycle 5
T_spc
T_splo
T_spis T_spih
T_spdo
Table 47 PROM Interface Timing Description
SYMBOL PARAMETER
MIN
TYP
Tspc
SPCK Cycle Time 40.0
Tspis SPDI Setup
10.0
Tspih SPDI Hold
0.0
Tsplo SPLD Output Tsc
Tspdo SPDO Output Tsc
MAX
UNIT
ns
ns
ns
Tsc + 3.0
ns
Tsc + 3.0
ns
03