C-3E Datasheet, PDF (39/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

Pin Descriptions Grouped by Function
39
Table 12 Gigabit Ethernet and Fibre Channel TBI Signals Example (continued)
SIGNAL NAME* PIN #† TOTAL TYPE
I/O LABEL
SIGNAL DESCRIPTION
CPn+1_3
CPn+1_4
CPn+1_5
CPn+1_6
CPn+2_0
CPn+2_1
CPn+2_2
CPn+2_3
CPn+2_4
CPn+2_5
CPn+2_6
CPn+3_0
CPn+3_1
CPn+3_2
CPn+3_3
CPn+3_4
CPn+3_5
CPn+3_6
TOTAL PINS
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
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LVTTL
LVTTL
LVTTL
LVTTL
nc
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
nc
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
O_PU TXD(4)
O_PD TXD(3)
O_PU TXD(2)
O_PU TXD(0)
nc_PD nc
I_PU RCLK
I_PD RXD(9)
I_PU RXD(8)
I_PD RXD(7)
I_PU RXD(6)
I_PU RXD(1)
nc_PD nc
I_PU RCLKN
I_PD RXD(5)
I_PU RXD(4)
I_PD RXD(3)
I_PU RXD(2)
I_PU RXD(0)
Transmit Data
Transmit Data
Transmit Data
Transmit Data (ten bits wide, first on wire)
nc
Receive Clock (62.5 MHz)
Receive Data (ten bits wide, last on wire)
Receive Data
Receive Data
Receive Data
Receive Data
nc
Receive Clock Inverted
Receive Data
Receive Data
Receive Data
Receive Data
Receive Data (ten bits wide, first on wire)
* _{n can be 0, or 4.}
† _{Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.}
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