C-3E Datasheet, PDF (80/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

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CHAPTER 3: ELECTRICAL SPECIFICATIONS
Clock Timing
Specifications
Cycle 1
The system clock timing is shown in Figure 13 and described in Table 37.
Figure 13 System Clock Timing Diagram
Cycle 2
Cycle 3
Cycle 4
Cycle 5
SCLK
SCLKX
T_sc
T_sh
T_sl
CCLKn
T_ccN
T_cch
T_ccl
Table 37 System Clock Timing Description
SYMBOL PARAMETER
MIN
TYP MAX UNIT COMMENT
Tsc
System Cycle Time 3.76
ns 180MHz core clock
Tsh
Sys Clk High Pulse 45
55
Duty cycle*
Tsl
Sys Clk Low Pulse 45
55
Duty cycle*
Tcc0
CCLK0 Cycle Time
6.43
ns †
Tcc1
CCLK1 Cycle Time
6.43
ns †
Tcc2
CCLK2 Cycle Time
6.43
ns †
Tcc3
CCLK3 Cycle Time
6.43
ns †
Tcch
CCLKm High Time 40%
60%
% cycle pulse is high
Tccl
CCLKm Low Time 40%
60%
% cycle pulse is low
* _{Pulse duty cycle measured at crossing voltage of SCLK/SCLKX}
† _{The frequencies specified for CCLK0 - CCLK3 allow full flexibility for the C-3e NP. It is also possible to use one}
or more CCLKn inputs for other frequencies; contact your Motorola representative for more information.
C3EN