C-3E Datasheet, PDF (67/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

JTAG Support
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JTAG Support
The C-3e NP contains JTAG test logic compliant with the IEEE 1149.1 specification. All
required public instructions are implemented, as well as some optional instructions. This
section contains information regarding the pinout, instructions, identification codes, and
boundary scan cell types.
Pinout The C-3e NP uses the standard JTAG pins including the optional test reset pin. Table 27
describes the pins and their functions.
JTAG Data Registers The C-3e NP contains the standard internal registers as specified in IEEE 1149.1. These
registers are described in Table 29.
Table 29 JTAG Internal Register Descriptions
REGISTER NAME
Bypass
Boundary
Device Identification
REGISTER LENGTH
1
1549
32
DESCRIPTION
Standard JTAG bypass register
Boundary Scan Register
Standard JTAG IDCODE Register
Boundary Scan Restriction SCLK/SCLKX inputs must not toggle when exercising the boundary scan function for JTAG.
Boundary Scan Cell Types
The C-3e NP boundary scan register contains only two cell types. All input cells are observe
only cells of type BC_4. All enable and output cells are standard cells of type BC_1. In IEEE
1149.1-1990 specification, the BC_4 cell is shown in Figure 7 and the BC_1 cell is shown in
Figure 8.
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