C-3E Datasheet, PDF (75/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

Power and Thermal Characteristics
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Power and Thermal
Characteristics
Table 36 provides the derived power and thermal characteristics for the production
version of the C-3e NP.
Table 36 C-3e Network Processor Power and Thermal Characteristics
PARAMETER
MIN TYP MAX UNITS TEST CONDITIONS
Power Dissipation, P_D
2.5 5.5 7.5 W
180MHz core clock
See Note below
Maximum Junction
Temperature, T_J
Thermal Resistance, junction
to case, θ_JC
Thermal Resistance, junction
to printed circuit board, θ_JB
125 ^oC
See Note below
<0.1
o_{C/W See Note below}
5.5
o_{C/W See Note below}
Table 36 note: Power dissipation values assume the following conditions:
• BMU memory operating at 125MHz
• TLU memory operating at 125MHz
• QMU operating at 150MHz
• VDD = 1.1V, VDD33/VDDT = 3.3V, TJ at approximately 50°C for typical values. VDD and
VDD33/VDDT are 5% higher for maximum values
• “Minimum” PD based on idle condition (clocks running and no programs executing)
• “Typical” PD based on test application that implements Fast Ethernet forwarding
actively running on all CPs
• “Maximum” PD based on maximum consumption for any high-bandwidth
communications application executing on all CPs, FP, and XP
Thermal Management
Information
This section provides thermal management information for the ceramic ball grid array
(CBGA) package for air-cooled applications. Proper thermal control design is primarily
dependent on the system-level design—the heat sink, airflow, and thermal interface
material. To reduce the die-junction temperature, heat sinks may be attached to the
package by several methods—spring clip to holes in the printed-circuit board or package,
and mounting clip and screw assembly (refer to Figure 10); however, due to the potential
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