C-3E Datasheet, PDF (44/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

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CHAPTER 2: SIGNAL DESCRIPTIONS
Table 15 PCI Signals (continued)
SIGNAL NAME
PGNTX
PIDSEL
PINTA
TOTAL PINS
PIN #
AA8
AA5
AC1
TOTAL TYPE I/O SIGNAL DESCRIPTION
1
I_PD
I
Initiator bus grant (arbitration)
1
PCI I Initialization device select
1
PCI O Interrupt
50
Serial Interface Signals
The Serial interface is a bidirectional two-wire serial bus. It can use one of the following
formats:
• An 8bit data format followed by an acknowledge bit, which supports transfers at up to
400kbps (low speed).
• a 16bit IEEE 802.3 MDIO data format with 10bits of addressing, which supports
transfers up to 25MHz (high speed).
The signals and pins are identical for both the high and low speed protocols.
Which of the two data rates used is selected by the state of the PROM interface’s SPLD
signal that is asserted while the PROM interface is idle. When SPLD is asserted HI the low
speed serial bus protocol is selected and when SPLD is asserted LOW the MDIO protocol is
selected.
The bus only supports a single master hierarchy that can operate as either a receiver or a
transmitter.
Both SIDA and SICL are bidirectional lines that are connected, through a pull-up resistor,
to a positive supply voltage. When the bus is free, both lines are HIGH. The output stages
of the devices connected to the bus must have either an open-drain or open-collector in
order to perform the wired-AND function required for its arbitration mechanism.
Table 16 Serial Interface Signals
SIGNAL NAME
SICL
SIDA
TOTAL PINS
PIN #
AA1
AA4
TOTAL TYPE
1
LVTTL
1
LVTTL
2
I/O SIGNAL DESCRIPTION
I_PD/O Serial Clock line
I_PD/O Serial Data line
C3EN