C-3E Datasheet, PDF (101/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

AC Timing Specifications 101
Table 55 QMU to Q-5/Q-3 (External Mode) Timing Description
SYMBOL PARAMETER
Tqec QMU External Cycle Time
Tqep QMU CLKA-CLKB delta
between rising edges
Tqes QMU Input Data Setup
Tqeh QMU Input Data Hold
Tqeo QMU Data Output
MIN TYP MAX UNIT COMMENT
10.0
ns QACLKO/QBCLKO
derived from
QACLKI/QBCLKI
4.8
ns
0.6
ns
0.8
ns
-.85
1.3 ns Determines valid time
for data from each clock
rising edge
Table 56 Signal Groups in QMU to Q-5/Q-3 (External Mode) Timimg Diagrams
SIGNAL GROUP
Input Clocks (QnCLKI)
Output Clocks (QnCLKO)
Input Data (DQDATA)
Output Data (NQDATA)
INCLUDED SIGNALS
QACLKI, QBCLKI
QACLKO, QBCLKO
QD0-23, QARDY, QDPL, QDPH, QNQRDY, QDQPAR
QA0-16, QWEX, QD24-31
03