C-3E Datasheet, PDF (81/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

AC Timing Specifications
81
CP Timing Specifications
This section describes the timing for the following CP interfaces:
• DS1/DS3
• 10/100 Ethernet
• Gigabit Ethernet
• OC-3
• OC-12
DS1/DS3 Timing Specifications
The DS1/DS3 interface timing is shown in Figure 14 and described in Table 38.
Figure 14 DS1/DS3 Ethernet Timing Diagram
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
CPn_0 (TCLK)
CPn_2/3 (Tx)
T_cdt
T_cdo
CPn_1 (RCLK)
CPn_4/5 (Rx)
Cycle 2
T_cdr
Cycle 3
Cycle 4
Cycle 5
T_cds T_cdh
Table 38 DS1/DS3 Ethernet Timing Description
SYMBOL
Tcdt
Tcdo
Tcdr
PARAMETER
DS1/DS3 Transmit Cycle Time
DS1/DS3 Output Time
DS1/DS3 Receive Cycle Time
MIN TYP
MAX
UNIT
647/22.4
ns
3.0/3.0
400/15.0 ns
647/22.4
ns
03