C-3E Datasheet, PDF (45/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

Pin Descriptions Grouped by Function
45
PROM Interface Signals
The PROM interface is a low speed I/O port that allows the C-3e NP to communicate
through external logic to PROM. The PROM clock is ¹/₂ to ¹/₁₆ the core clock rate.The
maximum PROM size addressable is 4MBytes, and must use a “by 16” part. The PROM
signals are listed in Table 17.
Table 17 PROM Interface Signals
SIGNAL
NAME
SPDO
SPDI
SPLD
PIN #
Y5
Y6
Y7
SPCK
Y8
TOTAL PINS
TOTAL TYPE I/O SIGNAL DESCRIPTION
1
LVTTL O Serial Data Out
1
LVTTL I_PD Serial Data In
1
LVTTL O When load is asserted on a positive clock
edge, the external logic performs a parallel
load. On each positive clock edge when
load is de-asserted, the shift registers shift.
When the PROM interface is idle:
• if SPLD is asserted HI it indicates low
speed serial protocol,
• if asserted LOW it indicates MDIO serial
protocol.
1
LVTTL O Clock
4
Figure 5 shows the connections between the PROM Interface and external board logic.
The application is required to provide an external shift register with parallel-in and
parallel-out capabilities, and a parallel load register. Both devices should be
positive-edge-triggered and perform a parallel load whenever SPLD is asserted. When
SPLD is deasserted the shift register shifts.
03