C-3E Datasheet, PDF (94/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

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CHAPTER 3: ELECTRICAL SPECIFICATIONS
BMU Timing
Specifications
The BMU timing specifications are shown in Figure 24 and described in Table 49.
The BMU synchronous DRAM interface is PC100-compliant and designed to work with
industry standard SDRAM components with 12 or fewer address lines. The information
below is intended to provide the output, setup, and hold data required to design this
interface without duplicating the transaction waveform diagrams in SDRAM data sheets.
Figure 24 BMU Timing Diagram
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
MDCLK
M_ctl
MAn
MDn
(output)
MDn
(input)
T_mdo
T_mc
T_mco
T_mao
T_mdz
T_mdv
T_mds
T_mdh
Table 49 BMU Timing Description
SYMBOL PARAMETER
MIN TYP
Tmc
BMU Cycle Time
8.0
Tmco BMU Ctrl Output
0.8
Tmao BMU Addr Output
0.8
Tmds BMU Data Setup
0.5
Tmdh BMU Data Hold
1.1
Tmdo BMU Data Output
0.8
Tmdz BMU Data Clk to Tri*
0.8
Tmdv BMU Data Clk to Driven* 0.8
* _{Not fully tested, values based on design/characterization.}
MAX UNIT
ns
3.9 ns
3.9 ns
ns
ns
4.5 ns
4.5 ns
4.5 ns
C3EN