C-3E Datasheet, PDF (54/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

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CHAPTER 2: SIGNAL DESCRIPTIONS
QMU SRAM (Internal The QMU signals are described in Table 24.
Mode) Interface Signals
Table 24 QMU SRAM (Internal Mode) Interface Signals
SIGNAL NAME
QA0 - QA16
QD0 - QD31
QDQPAR
QARDY
QNQRDY
QWEX
QBCLKO
QBCLKI
QACLKO
QACLKI
QDPL
QDPH
TOTAL PINS
PIN #
TOTAL TYPE
D10, C10, A10, F11, E11, D11, C11, B11, A11, F12, 17
E12, D12, C12, A12, F13, E13, D13
LVTTL
F1, E1, D1, C1, B1, F2, E2, C2, A2, E3, D3, C3, B3, A3, 32
D4, B4, A4, E5, D5, C5, B5, A5, E6, C6, A6, E7, D7,
C7, B7, A7, E8, D8
LVTTL
C8
1
LVTTL
F10
1
LVTTL
A9
1
LVTTL
E10
1
LVTTL
B8
1
LVTTL
A8
1
LVTTL
F9
1
LVTTL
E9
1
LVTTL
C9
1
LVTTL
B9
1
LVTTL
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I/O SIGNAL DESCRIPTION
O Address [16:0]
I_PD/O Data
I_PD nc
I_PD nc
I_PD nc
O Write Enable
O nc
I_PD nc
O nc
I_PD Input Clock
I_PD/O Data Parity Low
I_PD/O Data Parity High
C3EN