C-3E Datasheet, PDF (55/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

Pin Descriptions Grouped by Function
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QMU to Q-5/Q-3 (External The QMU to Q-5/Q-3 signals are described in Table 25.
Mode) Interface Signals
Table 25 QMU to Q-5/Q-3 (External Mode) Interface Signals
SIGNAL NAME
QA0 - QA15
QA16
QD0 - QD23
QD24 - QD31
QDQPAR
QARDY
QNQRDY
QWEX
QBCLKO
QBCLKI
QACLKO
QACLKI
QDPL
QDPH
TOTAL PINS
PIN #
TOTAL TYPE I/O
D10, C10, A10, F11, E11, D11, C11, B11, A11, 16
F12, E12, D12, C12, A12, F13, E13
LVTTL O
D13
1
LVTTL O
F1, E1, D1, C1, B1, F2, E2, C2, A2, E3, D3, C3, 24
B3, A3, D4, B4, A4, E5, D5, C5, B5, A5, E6, C6
LVTTL I_PD
A6, E7, D7, C7, B7, A7, E8, D8
C8
F10
A9
8
LVTTL I_PD
1
LVTTL I_PD
1
LVTTL I_PD
1
LVTTL O
E10
1
LVTTL O
B8
1
LVTTL O
A8
1
LVTTL I_PD
F9
1
LVTTL O
E9
1
LVTTL I_PD
C9
1
LVTTL O
B9
1
LVTTL O
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SIGNAL DESCRIPTION
Enqueue Data [8:23]
Enqueue Parity
Dequeue Data [0:23]
Enqueue Data [0:7]
Dequeue Parity
Dequeue Ack Ready
Enqueue Ready
Dequeue Ready
Output ClockB
Input ClockB
Output ClockA
Input ClockA
Dequeue Ack [0]
Dequeue Ack [1]
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