C-3E Datasheet, PDF (53/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

Pin Descriptions Grouped by Function
53
TLU SRAM Interface The TLU SRAM interface supports up to 128MBytes of SRAM at frequencies to 125MHz
Signals _{using LVTTL signaling levels (in single bank-mode only) and SRAM technologies up to}
64Mbits. The TLU SRAM interface signals are described in Table 23.
Table 23 TLU SRAM Interface Signals
SIGNAL NAME
TD0 - TD63
TA0 - TA21
TPAR0 - TPAR3
TCE0X - TCE3X
TWE0X - TWE3X
TCLKI
TOTAL PINS
PIN #
TOTAL
F3, F4, F5, F6, F7, F8, G1, G3, G4, G5, G7, G8, H1, H2, 64
H3, H5, H6, H7, H8, J1, J2, J3, J5, J6, J7, J8, K1, K3,
K4, K5, K7, K8, L1, L2, L3, L4, L5, L6, L7, L8, M1, M2,
M3, M5, M6, M7, M8, N1, N2, N3, N4, N5, N6, N7,
N8, P1, P3, P4, P5, P7, P8, R1, R2, R3
U2, U3, U4, U5, U6, U7, U8, V1, V3, V4, V5, V7, V8, 22
W1, W2, W3, W5, W6, W7, W8, Y1, Y2
T1, T2, T3, T5
4
T6, T7, T8, U1
4
R5, R6, R7, R8
4
R4
1
99
TYPE
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
I/O SIGNAL DESCRIPTION
I_PD/O TLU Memory Data
O_PD TLU Memory Address
I_PD/O Word Data Parity (i.e. TPAR0 across
TD15:0)
O_PD TLU Memory Chip Enable
O_PD TLU Memory Write Enable
I_PD TLU Clock Input
03