C-3E Datasheet, PDF (96/114 Pages) Freescale Semiconductor, Inc – C-3e NETWORK PROCESSOR SILICON REVISION A1

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CHAPTER 3: ELECTRICAL SPECIFICATIONS
TLU Timing Specifications The TLU timing specifications are shown in Figure 25 and described in Table 51.
Figure 25 TLU Timing Diagram
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
TCLKI
T_ctl
TAn
TDn
(output)
T_tdo
TDn
(input)
T_tc
T_tco
T_tao
T_tdz
T_tdv
Table 51 TLU Timing Description
SYMBOL PARAMETER
Ttc
TLU Cycle Time
MIN TYP
8.0
Ttco
TLU Ctrl Output
0.8
Ttao
TLU Addr Output
0.8
Ttds
TLU Data Setup
1.0
Ttdh
TLU Data Hold
1.2
Ttdo
TLU Data Output
0.8
Ttdz
TLU Data Clk to Tri*
0.8
Ttdv
TLU Data Clk to Driven* 0.8
* _{Not fully tested, values based on design/characterization.}
T_tds T_tdh
MAX UNIT
ns
3.9 ns
3.9 ns
ns
ns
4.2 ns
4.2 ns
4.2 ns
C3EN