MC9328MX1_06 Datasheet, PDF (96/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

5 Pin-Out and Package Information
Table 44 illustrates the package pin assignments for the 256-pin MAPBGA package. For a complete listing of signals, see the Signal
Multiplexing Table 3 on page 11.
Table 44. i.MX1 256 MAPBGA Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
NVSS
SD_DAT3 SD_CLK
NVSS
USBD_
AFE
NVDD4
NVSS
UART1_
RTS
UART1_
RXD
NVDD3
BT5
BT3
QVDD4
RVP
UIP
N.C.
A
B
A24
SD_DAT1 SD_CMD SIM_TX
USBD_
ROE
USBD_VP SSI_RXCLK SSI_TXCLK
SPI1_
SCLK
BT11
BT7
BT1
QVSS
RVM
UIN
N.C.
B
C
A23
D31
SD_DAT0 SIM_PD
USBD_
RCV
UART2_
CTS
UART2_
RXD
SSI_
RXFS
UART1_
TXD
BTRFGND
BT8
BTRFVDD
N.C.
AVDD2¹
VSS
R1B
C
D
A22
D30
D29
SIM_SVEN
USBD_
SUSPND
USBD_
VPO
USBD_
VMO
SSI_RXDAT
SPI1_
SPI_RDY
BT13
BT6
N.C.
N.C.
N.C.
R1A
R2B
D
E
A20
A21
D28
D26
SD_DAT2 USBD_VM
UART2_
RTS
SSI_TXDAT
SPI1_SS
BT12
BT4
N.C.
N.C.
PY2
PX2
R2A
E
F
A18
D27
D25
A19
A16
SIM_RST
UART2_
TXD
SSI_TXFS
SPI1_
MISO
BT10
BT2
REV
PY1
PX1
LSCLK SPL_SPR F
G
A15
A17
D24
D23
D21
SIM_RX
SIM_CLK
UART1_
CTS
SPI1_
MOSI
BT9
CLS
CONTRAST ACD/OE
LP/
HSYNC
FLM/
VSYNC
LD1
G
H
A13
D22
A14
D20
NVDD1
NVDD1
NVSS
QVSS
QVDD1
PS
LD0
LD2
LD4
LD5
LD9
LD3
H
J
A12
A11
D18
D19
NVDD1
NVDD1
NVSS
NVDD1
NVSS
NVSS
LD6
LD7
LD8
LD11
QVDD3
QVSS
J
K
A10
D16
A9
D17
NVDD1
NVSS
NVSS
NVDD1
NVDD2
NVDD2
LD10
LD12
LD13
LD14
TMR2OUT
LD15
K
L
A8
M
A5
N
A4
P
A3
A7
D13
D15
D14
NVDD1
NVSS
CAS
TCK
TIN
PWMO CSI_MCLK CSI_D0
CSI_D1
CSI_D2
CSI_D3 L
D12
D11
EB1
D10
A6
SDCLK
NVSS
RW
MA10
RAS
RESET_IN
BIG_
ENDIAN
CSI_D4
CSI_
HSYNC
CSI_VSYNC
CSI_D6
CSI_D5 M
D7
A0
D4
PA17
D1
DQM1
RESET_SF²
RESET_
OUT
BOOT2
CSI_
PIXCLK
CSI_D7
TMS
TDI
N
D9
EB0
CS3
D6
ECB
D2
D3
DQM3
SDCKE1 BOOT3
BOOT0
TRST
I2C_SCL I2C_SDA XTAL32K P
R
EB2
EB3
A1
CS4
D8
D5
LBA
BCLK³
D0
DQM0
SDCKE0
POR
BOOT1
TDO
QVDD2 EXTAL32K R
T
NVSS
A2
OE
CS5
CS2
CS1
CS0
MA11
DQM2
SDWE
CLKO
AVDD1 TRISTATE EXTAL16M XTAL16M
QVSS
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1 _{ASP signals are clamped by AVDD2 to prevent ESD (Electrostatic Discharge) damage. AVDD2 must be greater than QVDD to keep diodes reversed-biased.}
2 _{This signal is not used and should be floated in an actual application.}
3 _{burst clock}