MC9328MX1_06 Datasheet, PDF (4/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Signals and Connections
• Negated means that an asserted discrete signal changes logic state.
— Active low signals change from logic level zero to logic level one.
— Active high signals change from logic level one to logic level zero.
• LSB means least significant bit or bits, and MSB means most significant bit or bits. References to
low and high bytes or words are spelled out.
• Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x
are hexadecimal.
2 Signals and Connections
Table 2 identifies and describes the i.MX1 processor signals that are assigned to package pins. The signals
are grouped by the internal module that they are connected to.
Table 2. i.MX1 Signal Descriptions
Signal Name
Function/Notes
A[24:0]
D[31:0]
EB0
EB1
EB2
EB3
OE
CS [5:0]
ECB
LBA
BCLK (burst clock)
RW
DTACK
BOOT [3:0]
SDBA [4:0]
External Bus/Chip-Select (EIM)
Address bus signals
Data bus signals
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24].
Byte Strobe—Active low external enable byte signal that controls D [23:16].
Byte Strobe—Active low external enable byte signal that controls D [15:8].
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0].
Memory Output Enable—Active low output enables external data bus.
Chip-Select—The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the
Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected.
Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an
on-going burst sequence and initiate a new (long first access) burst sequence.
Active low signal sent by a flash device causing the external burst device to latch the starting burst
address.
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE input
signal by external DRAM.
DTACK signal—The external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK signal after 1022 clock counts have elapsed.
Bootstrap
System Boot Mode Select—The operational system boot mode of the i.MX1 processor upon system
reset is determined by the settings of these pins.
SDRAM Controller
SDRAM non-interleave mode bank address multiplexed with address signals A [15:11]. These signals
are logically equivalent to core address p_addr [25:21] in SDRAM cycles.
MC9328MX1 Technical Data, Rev. 7
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Freescale Semiconductor