MC9328MX1_06 Datasheet, PDF (68/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
Table 27. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued)
Symbol
Description
Minimum Corresponding Register Value Unit
T8 SCLK to valid LD data
-3
3
ns
T9 End of HSYN idle2 to VSYN edge
(for non-display region)
2
2
Ts
T9 End of HSYN idle2 to VSYN edge
(for Display region)
1
1
Ts
T10 VSYN to OE active (Sharp = 0) when VWAIT2 = 0
1
1
Ts
T10 VSYN to OE active (Sharp = 1) when VWAIT2 = 0
2
2
Ts
Note:
• Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.
• VSYN, HSYN and OE can be programmed as active high or active low. In Figure 46, all 3 signals
are active low.
• The polarity of SCLK and LD[15:0] can also be programmed.
• SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period.
In Figure 46, SCLK is always active.
• For T9 non-display region, VSYN is non-active. It is used as an reference.
• XMAX is defined in pixels.
4.10 Multimedia Card/Secure Digital Host Controller
The DMA interface block controls all data routing between the external data bus (DMA access), internal
MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that
monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the
MMC/SD module (inner system) and the application (user programming).
3a
12
3b
4b
Bus Clock
4a
5a
5b
CMD_DAT Input
Valid Data
Valid Data
CMD_DAT Output
7
Valid Data
Valid Data
6a
6b
Figure 47. Chip-Select Read Cycle Timing Diagram
MC9328MX1 Technical Data, Rev. 7
68
Freescale Semiconductor