MC9328MX1_06 Datasheet, PDF (59/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

4.4.4 Non-TFT Panel Timing
T1
VSYN
Functional Description and Application Information
T1
T2
T3
XMAX
T4
T2
HSYN
SCLK
Ts
LD[15:0]
Figure 33. Non-TFT Panel Timing
Table 17. Non TFT Panel Timing Diagram
Symbol
Parameter
Allowed Register
Minimum Value^{1, 2}
Actual Value
Unit
T1
HSYN to VSYN delay³
0
HWAIT2+2
Tpix⁴
T2 HSYN pulse width
0
HWIDTH+1
Tpix
T3 VSYN to SCLK
–
0 ≤ T3 ≤ Ts⁵
–
T4 SCLK to HSYN
0
HWAIT1+1
Tpix
1 _{Maximum frequency of LCDC_CLK is 48 MHz, which is controlled by Peripheral Clock Divider Register.}
2 _{Maximum frequency of SCLK is HCLK / 5, otherwise LD output will be wrong.}
3 _{VSYN, HSYN and SCLK can be programmed as active high or active low. In the above timing diagram, all}
these 3 signals are active high.
4 _{Tpix is the pixel clock period which equals LCDC_CLK period * (PCD + 1).}
5 _{Ts is the shift clock period. Ts = Tpix * (panel data bus width).}
4.5 Pen ADC Specifications
The specifications for the pen ADC are shown in Table 18 through Table 20.
Table 18. Pen ADC System Performance
Full Range Resolution¹
Non-Linearity Error¹
Accuracy ¹
13 bits
4 bits
9 bits
1 _{Tested under input = 0~1.8V at 25°C}
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
59