MC9328MX1_06 Datasheet, PDF (80/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
SDCLK
CS
RAS
CAS
1
3
2
6
WE
ADDR
DQ
5
4
/ BA
ROW/BA
7
COL/BA
8
9
DATA
DQM
Figure 58. SDRAM Write Cycle Timing Diagram
Table 34. SDRAM Write Timing Parameter Table
Ref No.
Parameter
1.8 ± 0.1 V
Minimum Maximum
3.0 ± 0.3 V
Unit
Minimum Maximum
1 SDRAM clock high-level width
2.67
–
4
–
ns
2 SDRAM clock low-level width
6
–
4
–
ns
3 SDRAM clock cycle time
11.4
–
10
–
ns
4 Address setup time
3.42
–
3
–
ns
5 Address hold time
6 Precharge cycle period¹
2.28
–
2
–
ns
t_RP2
–
t_RP2
–
ns
7 Active to read/write command delay
t_RCD2
–
t_RCD2
–
ns
8 Data setup time
4.0
–
2
–
ns
9 Data hold time
2.28
–
2
–
ns
1 _{Precharge cycle timing is included in the write timing diagram.}
2 _{tRP and tRCD = SDRAM clock cycle time. These settings can be found in the MC9328MX1 reference manual.}
MC9328MX1 Technical Data, Rev. 7
80
Freescale Semiconductor