MC9328MX1_06 Datasheet, PDF (32/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
4.4.2.2 WAIT Read Cycle DMA Enabled
Address
2
CS5
1
programmable
EB
min 0ns
OE
4
9
10
3
6
RW (logic high)
WAIT
DATABUS
nput to
MX1)
5
7
11
8
12
Figure 7. DTACK WAIT Read Cycle DMA Enabled
Table 14. DTACK WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
Number
Characteristic
1
OE and EB assertion time
2
CS pulse width
3
OE negated before CS5 is negated
4
Address inactived before CS negated
5
Wait asserted after CS5 asserted
6
Wait asserted to OE negated
7
Data hold timing after OE negated
8
Data ready after wait is asserted
9
CS deactive to next CS active
10
OE negate after EB negate
11
Wait becomes low after CS5 asserted
3.0 ± 0.3 V
Unit
Minimum
Maximum
See note 2
3T
1.5T+0.24
–
–
2T+2.2
T-1.86
–
T
0.5
0
–
ns
–
ns
1.5T+0.85
ns
0.93
ns
1020T
ns
3T+7.17
ns
–
ns
T
ns
–
ns
1.5
ns
1019T
ns
MC9328MX1 Technical Data, Rev. 7
32
Freescale Semiconductor