MC9328MX1_06 Datasheet, PDF (35/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
Table 16. WAIT Write Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
1
CS5 assertion time
See note 2
–
ns
2
EB assertion time
See note 2
–
ns
3
CS5 pulse width
3T
–
ns
4
RW negated before CS5 is negated
2.5T-0.29
2.5T+0.68
ns
5
Address inactived after CS negated
–
0.93
ns
6
Wait asserted after CS5 asserted
–
1020T
ns
7
Wait asserted to RW negated
T+2.15
2T+7.34
ns
8
Data hold timing after RW negated
24.87
–
ns
9
Data ready after CS5 is asserted
–
T
ns
10
CS deactive to next CS active
T
–
ns
11
EB negate after CS negate
1.5T+0.74
1.5T+2.35
12
Wait becomes low after CS5 asserted
0
1019T
ns
13
Wait pulse width
1T
1020T
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. CS5 assertion can be controlled by CSA bits. EB assertion also can be programmable by WEA bits in CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4.The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
4.4.3 EIM External Bus Timing
The External Interface Module (EIM) is the interface to devices external to the i.MX1, including
generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown
in Figure 5, and Table 12 defines the parameters of signals.
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
35