MC9328MX1_06 Datasheet, PDF (67/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
Table 26. LCDC SCLK Timing Parameter Table
Ref No.
Parameter
1 SCLK to LD valid
3.0 ± 0.3 V
Minimum
–
Maximum
Unit
2
ns
VSYN
HSYN
OE
LD[15:0]
Non-display
T1
T3
T2
Line Y
Display region
T4
Line 1
Line Y
T5
T6
XMAX
T7
HSYN
SCLK
OE
T8
LD[15:0]
(1,1) (1,2)
(1,X)
VSYN
T9
T10
Figure 46. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing
Table 27. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing
Symbol
Description
T1 End of OE to beginning of VSYN
T2 HSYN period
T3 VSYN pulse width
T4 End of VSYN to beginning of OE
T5 HSYN pulse width
T6 End of HSYN to beginning to T9
T7 End of OE to beginning of HSYN
Minimum Corresponding Register Value Unit
T5+T6
(VWAIT1·T2)+T5+T6+T7+T9
Ts
+T7+T9
XMAX+5
XMAX+T5+T6+T7+T9+T10
Ts
T2
VWIDTH·(T2)
Ts
2
VWAIT2·(T2)
Ts
1
HWIDTH+1
Ts
1
HWAIT2+1
Ts
1
HWAIT1+1
Ts
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
67