MC9328MX1_06 Datasheet, PDF (33/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
Table 14. DTACK WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
12
Wait pulse width
1T
1020T
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
4.4.2.3 WAIT Write Cycle without DMA
Address
1
CS5
2
EB
RW
3
programmable
min 0ns
programmable
min 0ns
5
10
4
7
OE(logic ^high)
WAIT
DATABUS
(output from
i.MX1)
6
11
9
8
12
Figure 8. WAIT Write Cycle without DMA
Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
Number
Characteristic
1
CS5 assertion time
2
EB assertion time
3
CS5 pulse width
4
RW negated before CS5 is negated
5
RW negated to Address inactive
6
Wait asserted after CS5 asserted
3.0 ± 0.3 V
Unit
Minimum
Maximum
See note 2
See note 2
3T
2.5T-0.29
67.28
–
–
ns
–
ns
–
ns
2.5T+0.68
ns
–
ns
1020T
ns
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
33