MC9328MX1_06 Datasheet, PDF (69/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
Table 28. SDHC Bus Timing Parameter Table
Ref
No.
Parameter
1 CLK frequency at Data transfer Mode
(PP)¹â€”10/30 cards
2 CLK frequency at Identification Mode²
3a Clock high time¹â€”10/30 cards
3b Clock low time¹â€”10/30 cards
4a Clock fall time¹â€”10/30 cards
4b Clock rise time¹â€”10/30 cards
5a Input hold time³â€”10/30 cards
5b Input setup time³â€”10/30 cards
6a Output hold time³â€”10/30 cards
6b Output setup time³â€”10/30 cards
7 Output delay time³
1 _{CL ≤ 100 pF / 250 pF (10/30 cards)}
2 _{CL ≤ 250 pF (21 cards)}
3 _{CL ≤ 25 pF (1 card)}
1.8 ± 0.1 V
Minimum
0
Maximum
25/5
3.0 ± 0.3 V
Minimum
0
Maximum
25/5
Unit
MHz
0
6/33
15/75
–
–
10.3/10.3
10.3/10.3
5.7/5.7
5.7/5.7
0
400
–
–
10/50
(5.00)³
14/67
(6.67)³
–
–
–
–
16
0
10/50
10/50
–
–
9/9
9/9
5/5
5/5
0
400
kHz
–
ns
–
ns
10/50
ns
10/50
ns
–
ns
–
ns
–
ns
–
ns
14
ns
4.10.1 Command Response Timing on MMC/SD Bus
The card identification and card operation conditions timing are processed in open-drain mode. The card
response to the host command starts after exactly N_ID clock cycles. For the card address assignment,
SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and
card response is NCR clock cycles as illustrated in Figure 48. The symbols for Figure 48 through
Figure 52 are defined in Table 29.
Table 29. State Signal Parameters for Figure 48 through Figure 52
Card Active
Host Active
Symbol
Definition
Symbol
Definition
Z
High impedance state
S
Start bit (0)
D
Data bits
T
Transmitter bit (Host = 1, Card = 0)
*
Repetition
P
One-cycle pull-up (1)
CRC Cyclic redundancy check bits (7 bits)
E
End bit (1)
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
69