MC9328MX1_06 Datasheet, PDF (63/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

2
BT CLK (BT1)
Functional Description and Application Information
FS (BT5)
1
PKT DATA (BT3)
7
34
Receive
RXTX_EN (BT9)
PKT DATA (BT2)
8
Transmit
5
6
Figure 37. MC13180 Data Bus Timing Diagram
Table 22. MC13180 Data Bus Timing Parameter Table
Ref No.
Parameter
Minimum Typical Maximum Unit
1
FrameSync setup time relative to BT CLK rising edge¹
–
4
–
ns
2
FrameSync hold time relative to BT CLK rising edge¹
–
12
–
ns
3
Receive Data setup time relative to BT CLK rising edge¹
–
6
–
ns
4
Receive Data hold time relative to BT CLK rising edge¹
–
13
–
ns
5
Transmit Data setup time relative to RXTX_EN rising edge²
172.5
–
192.5
µs
6 TX DATA period
1000 +/- 0.02
ns
7 BT CLK duty cycle
40
–
60
%
8 Transmit Data hold time relative to RXTX_EN falling edge
4
–
10
µs
1 _{Please refer to 2.4 GHz RF Transceiver Module (MC13180) Technical Data documentation.}
2 _{The setup and hold times of RX_TX_EN can be adjusted by programming Time_A_B register (0x00216050) and}
RF_Status (0x0021605C) registers.
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
63