MC9328MX1_06 Datasheet, PDF (77/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
Table 31. MSHC Signal Timing Parameter Table (Continued)
Ref
No.
Parameter
3.0 ± 0.3 V
Unit
Minimum Maximum
12 MS_SDIO output delay time^1,2
–
13 MS_SDIO input setup time for MS_SCLKO rising edge (RED bit = 0)³
18
14 MS_SDIO input hold time for MS_SCLKO rising edge (RED bit = 0)³
0
15 MS_SDIO input setup time for MS_SCLKO falling edge (RED bit = 1)⁴
23
16 MS_SDIO input hold time for MS_SCLKO falling edge (RED bit = 1)⁴
0
3
ns
–
ns
–
ns
–
ns
–
ns
1 _{Loading capacitor condition is less than or equal to 30pF.}
2 _{An external resistor (100 ~ 200 ohm) should be inserted in series to provide current control on the MS_SDIO pin,}
because of a possibility of signal conflict between the MS_SDIO pin and Memory Stick SDIO pin when the pin
direction changes.
3 _{If the MSC2[RED] bit = 0, MSHC samples MS_SDIO input data at MS_SCLKO rising edge.}
4 _{If the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge.}
4.12 Pulse-Width Modulator
The PWM can be programmed to select one of two clock signals as its source frequency. The selected
clock signal is passed through a divider and a prescaler before being input to the counter. The output is
available at the pulse-width modulator output (PWMO) external pin. Its timing diagram is shown in
Figure 56 and the parameters are listed in Table 32.
System Clock
PWM Output
2a
2b
4a
1
3b
3a
4b
Figure 56. PWM Output Timing Diagram
Table 32. PWM Output Timing Parameter Table
Ref No.
Parameter
1 System CLK frequency¹
2a Clock high time¹
2b Clock low time¹
3a Clock fall time¹
1.8 ± 0.1 V
Minimum
0
3.3
7.5
–
Maximum
87
–
–
5
3.0 ± 0.3 V
Minimum
0
5/10
5/10
–
Maximum
100
–
–
5/10
Unit
MHz
ns
ns
ns
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
77