MC9328MX1_06 Datasheet, PDF (90/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
Table 40. SSI (Port B Alternate Function) Timing Parameter Table (Continued)
Ref
No.
Parameter
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
28 STCK high to STXD high impedance
29 SRXD setup time before SRCK low
30 SRXD hold time after SRCK low
17.90
29.75
15.7
1.14
–
1.0
0
–
0
26.1
ns
–
ns
–
ns
Synchronous Internal Clock Operation (Port B Alternate Function²)
31 SRXD setup before STCK falling
32 SRXD hold after STCK falling
18.81
–
16.5
–
ns
0
–
0
–
ns
Synchronous External Clock Operation (Port B Alternate Function²)
33 SRXD setup before STCK falling
1.14
–
1.0
–
ns
34 SRXD hold after STCK falling
0
–
0
–
ns
1 _{All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync}
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
2 _{There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B}
alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary
function and Port B alternate function. When SSI signals are configured as inputs, the SSI module selects the input based on
FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function.
3 _{bl = bit length; wl = word length.}
Table 41. SSI 2 (Port C Alternate Function) Timing Parameter Table
Ref
No.
Parameter
1.8V +/- 0.10V
3.0V +/- 0.30V
Unit
Minimum Maximum Minimum Maximum
Internal Clock Operation¹ (Port C Alternate Function)²
1 STCK/SRCK clock period¹
2 STCK high to STFS (bl) high³
3 SRCK high to SRFS (bl) high³
4 STCK high to STFS (bl) low³
5 SRCK high to SRFS (bl) low³
6 STCK high to STFS (wl) high³
7 SRCK high to SRFS (wl) high³
8 STCK high to STFS (wl) low³
9 SRCK high to SRFS (wl) low³
95
–
83.3
1.7
4.8
1.5
-0.1
1.0
-0.1
3.08
5.24
2.7
1.25
2.28
1.1
1.71
4.79
1.5
-0.1
1.0
-0.1
3.08
5.24
2.7
1.25
2.28
1.1
10 STCK high to STXD valid from high impedance
14.93
16.19
13.1
11a STCK high to STXD high
1.25
3.42
1.1
–
ns
4.2
ns
1.0
ns
4.6
ns
2.0
ns
4.2
ns
1.0
ns
4.6
ns
2.0
ns
14.2
ns
3.0
ns
MC9328MX1 Technical Data, Rev. 7
90
Freescale Semiconductor