MC9328MX1_06 Datasheet, PDF (5/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Signal Name
SDIBA [3:0]
MA [11:10]
MA [9:0]
DQM [3:0]
CSD0
CSD1
RAS
CAS
SDWE
SDCKE0
SDCKE1
SDCLK
RESET_SF
EXTAL16M
XTAL16M
EXTAL32K
XTAL32K
CLKO
RESET_IN
RESET_OUT
POR
TRST
TDO
TDI
TCK
TMS
Signals and Connections
Table 2. i.MX1 Signal Descriptions (Continued)
Function/Notes
SDRAM interleave addressing mode bank address multiplexed with address signals A [19:16]. These
signals are logically equivalent to core address p_addr [12:9] in SDRAM cycles.
SDRAM address signals
SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected on
SDRAM cycles.
SDRAM data enable
SDRAM Chip-select signal which is multiplexed with the CS2 signal. These two signals are selectable
by programming the system control register.
SDRAM Chip-select signal which is multiplexed with CS3 signal. These two signals are selectable by
programming the system control register. By default, CSD1 is selected, so it can be used as boot
chip-select by properly configuring BOOT [3:0] input pins.
SDRAM Row Address Select signal
SDRAM Column Address Select signal
SDRAM Write Enable signal
SDRAM Clock Enable 0
SDRAM Clock Enable 1
SDRAM Clock
Not Used
Clocks and Resets
Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is shut
down.
Crystal output
32 kHz crystal input
32 kHz crystal output
Clock Out signal selected from internal clock signals.
Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all
modules (except the reset module and the clock control module) are reset.
Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from the
following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.
Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally
generated by an external RC circuit designed to detect a power-up event.
JTAG
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
Serial Output for test instructions and data. Changes on the falling edge of TCK.
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
Test Clock to synchronize test logic and control register access through the JTAG port.
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of
TCK.
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
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